Spartan-6 Clock Multiplier / Divider using PLL DCM

I started using Spartan-6 FPGA couple of weeks ago.  Going back to my old VHDL coding to be able to work on a custom application.
I needed to divide my input 100MHz CLK to run a task at 33MHz.  I know I should be able to do that with the PLL/DCM built in the Spartan-6.  But, I can not find any reference code to show what/how is this done in code.  How can I configure the PLL registers to divide/multiply and what is the labels I will be using to trigger to my task.

If someone out there able to explain that, I really would appreciate a lot.