Spartan-6 Clock Multiplier / Divider using PLL DCM

I started using Spartan-6 FPGA couple of weeks ago.  Going back to my old VHDL coding to be able to work on a custom application.
I needed to divide my input 100MHz CLK to run a task at 33MHz.  I know I should be able to do that with the PLL/DCM built in the Spartan-6.  But, I can not find any reference code to show what/how is this done in code.  How can I configure the PLL registers to divide/multiply and what is the labels I will be using to trigger to my task.

If someone out there able to explain that, I really would appreciate a lot.

FPGA SPARTAN-2 XC2S200 Tools

I am going back to my Digilab 2 FPGA Board that has Spartan-2 FPGA from Xilinx for a small project and proof of concept, but for my surprise, the new ISE Webpack from Xilinx does not support this chip anymore.  And, of-course, Digilent does not support it either,   is it discontinued board.  So, now what should I do?

I know this board is more than enough for what I am working on.  I got another board Nexys-3 that has Spartan-6 and it works so far great, but, is the Spartan-2 really un-usable now?  or, is someone out there can guide to and point me to a tool that I can use to program it with?

I am going to work on this task and try to see what I can do and find...